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FM18L08-70-SG データシート(PDF) 2 Page - Ramtron International Corporation

部品番号 FM18L08-70-SG
部品情報  256Kb Bytewide FRAM Memory
Download  13 Pages
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM18L08-70-SG データシート(HTML) 2 Page - Ramtron International Corporation

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This product conforms to specifications per the terms of the Ramtron
Ramtron International Corporation
standard warranty. The product has completed Ramtron’s internal
1850 Ramtron Drive, Colorado Springs, CO 80921
qualification testing and has reached production status.
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 3.4
July 2007
2 of 13
Address
Latch
A0-A14
CE
Control
Logic
WE
Row
Decoder
Block Decoder
Column Decoder
A0-A7
A8-A9
A10-A14
I/O Latch
Bus Driver
OE
32,768 x 8 FRAM Array
DQ0-7
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A14
Input
Address: The 15 address lines select one of 32,768 bytes in the FRAM array. The
address value is latched on the falling edge of /CE.
DQ0-7
I/O
Data: 8-bit bi-directional data bus for accessing the FRAM array.
/CE
Input
Chip Enable. /CE selects the device when low. Asserting /CE low causes the address
to be latched internally. Address changes that occur after /CE goes low will be
ignored until the next falling edge occurs.
/OE
Input
Output Enable: Asserting /OE low causes the FM18L08 to drive the data bus when
valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.
/WE
Input
Write Enable: Asserting /WE low causes the FM18L08 to write the contents of the
data bus to the address location latched by the falling edge of /CE.
VDD
Supply
Supply Voltage
VSS
Supply
Ground
Functional Truth Table
/CE
/WE
Function
H
X
Standby/Precharge
X
Latch Address (and Begin Write if /WE=low)
L
H
Read
L
Write
Note: The /OE pin controls only the DQ output buffers.


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