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FM21L16 データシート(PDF) 2 Page - Ramtron International Corporation |
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FM21L16 データシート(HTML) 2 Page - Ramtron International Corporation |
2 / 14 page FM21L16 - 128Kx16 FRAM Rev. 1.0 Sept. 2007 Page 2 of 14 CE Control Logic WE A(16:2) A(1:0) I/O Latch & Bus Driver OE DQ(15:0) 16K x 16 block 16K x 16 block 16K x 16 block 16K x 16 block 16K x 16 block 16K x 16 block 16K x 16 block 16K x 16 block A(16:0) Column Decoder UB, LB 2 ZZ Figure 1. Block Diagram Pin Description Pin Name Type Pin Description A(16:0) Input Address inputs: The 17 address lines select one of 131,072 words in the FRAM array. The lowest two address lines A(1:0) may be used for page mode read and write operations. /CE Input Chip Enable input: The device is selected and a new memory access begins when /CE is low and /ZZ is high. The entire address is latched internally on the falling edge of /CE. Subsequent changes to the A(1:0) address inputs allow page mode operation when /CE is low. /WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM21L16 to write the data on the DQ bus to the FRAM array. The falling edge of /WE latches a new column address for page mode write cycles. /OE Input Output Enable: When /OE is low, the FM21L16 drives the data bus when valid read data is available. Deasserting /OE high tri-states the DQ pins. /ZZ Input Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply current condition. Since this input is logically AND’d with /CE, /ZZ must be high for normal read/write operation. If unused, tie /ZZ to VDD. DQ(15:0) I/O Data: 16-bit bi-directional data bus for accessing the FRAM array. /UB Input Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z if /UB is high. /LB Input Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z if /LB is high. VDD Supply Supply Voltage: 3.3V VSS Supply Ground |
同様の部品番号 - FM21L16 |
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同様の説明 - FM21L16 |
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