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FM21L16-60-TG データシート(PDF) 10 Page - Ramtron International Corporation

部品番号 FM21L16-60-TG
部品情報  2Mbit FRAM Memory
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM21L16-60-TG データシート(HTML) 10 Page - Ramtron International Corporation

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 10 / 14 page
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FM21L16 - 128Kx16 FRAM
Rev. 1.0
Sept. 2007
Page 10 of 14
Power Cycle and Sleep Mode Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tPU
Power Up to First Access Time (after VTP is reached)
450
-
µs
tPD
Last Write (/WE high) to Power Down Time (prior to VTP)
0
-
µs
tVR
VDD Rise Time
50
-
µs/V
1,2
tVF
VDD Fall Time
100
-
µs/V
1,2
tZZH
/ZZ Active to DQ Hi-Z Time
-
20
ns
tWEZZ
Last Write to Sleep Mode Entry Time
0
-
µs
tZZL
/ZZ Active Low Time
1
-
µs
tZZEN
Sleep Mode Entry Time (/ZZ low to /CE don’t care)
-
0
µs
tZZEX
Sleep Mode Exit Time (/ZZ high to 1
st access after wakeup)
-
450
µs
Notes
1.
Slope measured at any point on VDD waveform.
2.
Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
0 to 3V
Input and Output Timing Levels
1.5V
Input Rise and Fall Times
3 ns
Output Load Capacitance
30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)


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