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FM24C16A データシート(PDF) 7 Page - Ramtron International Corporation

部品番号 FM24C16A
部品情報  16Kb FRAM Serial Memory
Download  12 Pages
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM24C16A データシート(HTML) 7 Page - Ramtron International Corporation

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FM24C16A
Rev 3.0
Mar. 2005
Page 7 of 12
The operation is now a current address read. This
operation is illustrated in Figure 9.
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM24C16
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Figure 7. Current Address Read
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM24C16
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Data Byte
A
Acknowledge
Figure 8. Sequential Read
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM24C16
Start
Address
Stop
No
Acknowledge
Data
Data Byte
A
Acknowledge
S
A
Slave Address
0
Word Address
A
Start
Address
Acknowledge
Figure 9. Selective (Random) Read
Endurance
The FM24C16A internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The FRAM
architecture is based on an array of rows and
columns. Rows are defined by A10-A3. Each access
causes an endurance cycle for a row. Endurance can
be optimized by ensuring frequently accessed data is
placed in different rows. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 3000 accesses per second to
the same row, 10 years time will elapse before 1
trillion endurance cycles occur.


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