データシートサーチシステム |
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FM24C256 データシート(PDF) 7 Page - Ramtron International Corporation |
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FM24C256 データシート(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24C256 Rev 3.1 May 2005 Page 7 of 12 S A Slave Address 1 Data Byte 1 P By Master By FM24C256 Start Address Stop Acknowledge No Acknowledge Data Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By FM24C256 Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By FM24C256 Start Address Stop No Acknowledge Data S A Slave Address 0 Address MSB A Start Address Acknowledge Address LSB A Figure 9. Selective (Random) Read Endurance A FRAM internally operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read and write access. The FRAM architecture is based on an array of rows and columns. Rows (A14-A6) are subdivided into 8 segments (A5-A3). Each access causes an endurance cycle for a row segment. In the FM24C256, there are 8 bytes per segment. Endurance can be optimized by ensuring frequently accessed data is located in different segments. Regardless, FRAM read and write endurance is effectively unlimited at the 1MHz two-wire speed. Even at 30 accesses per second to the same segment, 10 years time will elapse before 10 billion endurance cycles occur. |
同様の部品番号 - FM24C256_05 |
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同様の説明 - FM24C256_05 |
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