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FM24C512 データシート(PDF) 4 Page - Ramtron International Corporation

部品番号 FM24C512
部品情報  512Kb FRAM Serial Memory
Download  12 Pages
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM24C512 データシート(HTML) 4 Page - Ramtron International Corporation

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FM24C512
Rev. 1.0
Aug. 2006
Page 4 of 12
Stop
(Master)
Start
(Master)
7
Data bits
(Transmitter)
6
0
Data bit
(Transmitter)
Acknowledge
(Receiver)
Figure 3. Data Transfer Protocol
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24C512 must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM24C512 for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The Acknowledge takes place after the 8
th data bit
has been transferred in any transaction. During this
state the transmitter should release the SDA bus to
allow the receiver to drive it. The receiver drives the
SDA signal low to acknowledge receipt of the byte.
If the receiver does not drive SDA low, the condition
is a No-Acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge terminates the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C512
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24C512 to attempt to drive the
bus on the next clock while the master is sending a
new command such as Stop.
Slave Address
The first byte that the FM24C512 expects after a
Start condition is the Slave Address. As shown in
Figure 4, the Slave Address contains the Slave ID
(device type), the device select bits (A1, A2), the
MSB (A15) of the two-byte address, and a bit that
specifies if the transaction is a read or a write. Bits
7-4 define the device type and must be set to 1010b
for the FM24C512. These bits allow other types of
function types to reside on the 2-wire bus within an
identical address range. Bits 3-2 are the device
select bits which are equivalent to chip select bits.
They must match the corresponding value on the
external address pins to select the device. Up to four
FM24C512 devices can reside on the same two-wire
bus by assigning a different address to each. Bit 1 is
the most significant address bit and acts like a bank
select bit. This is important to understand when the
device automatically increments the address at the
7FFFh and FFFFh boundaries (covered in the next
section). Bit 0 is the read/write bit. A 1 indicates a
read operation, and a 0 indicates a write.
Figure 4. Slave Address
1
0
1
0
A2
R/W
Slave ID
7
6
5
4
3
2
1
0
A1
A15
Device
Select
Address
MSB


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