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FM24C256-SE データシート(PDF) 3 Page - Ramtron International Corporation |
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FM24C256-SE データシート(HTML) 3 Page - Ramtron International Corporation |
3 / 12 page FM24C256 Rev 3.1 May 2005 Page 3 of 12 Overview The FM24C256 is a serial FRAM memory. The memory array is logically organized as 32,768 x 8 bit memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C256 and a serial EEPROM relates to its superior write performance. Memory Architecture When accessing the FM24C256, the user addresses 32,768 locations each with 8 data bits. These data bits are shifted serially. The 32,768 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish from other non- memory devices), and an extended 16-bit address. Only the lower 15 bits are used by the decoder for accessing the memory. The upper address bit should be set to 0 for compatibility with higher density devices in the future. The memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. By the time a new bus transaction can be shifted into the part, a write operation is complete. This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C256 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since the write cycle is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM24C256 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is maintained within data sheet tolerances to prevent incorrect operation. Two-wire Interface The FM24C256 employs a bi-directional two-wire bus protocol using few pins and little board space. Figure 2 illustrates a typical system configuration using the FM24C256 in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24C256 is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including Start, Stop, Data bit, and Acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the Electrical Specifications section. Microcontroller SDA SCL FM24C256 A0 A1 A2 SDA SCL FM24C64 A0 A1 A2 VDD Rmin = 1.8 K Ω Rmax = tR/Cbus Figure 2. Typical System Configuration |
同様の部品番号 - FM24C256-SE |
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同様の説明 - FM24C256-SE |
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