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FM24C512-G データシート(PDF) 6 Page - Ramtron International Corporation

部品番号 FM24C512-G
部品情報  512Kb FRAM Serial Memory
Download  12 Pages
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM24C512-G データシート(HTML) 6 Page - Ramtron International Corporation

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FM24C512
Rev. 1.0
Aug. 2006
Page 6 of 12
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM24C512
Start
Address & Data
Stop
Acknowledge
Address LSB
A
X
A15
Figure 5. Single Byte Write
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM24C512
Start
Address & Data
Stop
Acknowledge
Address LSB
A
X
Data Byte
A
A15
Figure 6. Multiple Byte Write
Read Operation
There are two types of read operations. They are
current address read and selective address read. In a
current address read, the FM24C512 uses the internal
address latch to supply the address, but A15 must be
specified in the Slave Address byte. In a selective
read, the user performs a procedure to set the address
to a specific value.
Current Address & Sequential Read
As mentioned above the FM24C512 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. However, the address latch holds A(14:0),
so A15 must be specified. The system reads from the
address immediately following that of the last
operation.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving
the
complete
device
address,
the
FM24C512 will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address
counter will be incremented.
Each time the bus master acknowledges a byte, this
indicates that the FM24C512 should read out the next
sequential byte.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the FM24C512
attempts to read out additional data onto the bus. The
four valid methods are as follows.
1.
The bus master issues a no-acknowledge in the
9
th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
2.
The bus master issues a no-acknowledge in the
9
th clock cycle and a start in the 10th.
3.
The bus master issues a stop in the 9
th clock
cycle.
4.
The bus master issues a start in the 9
th clock
cycle.
The memory should be treated as two separate
address spaces, an upper and lower. If the internal
address reaches 7FFFh, it will wrap around to 0000h
on the next read cycle. Likewise if the internal
address reaches FFFFh, it will wrap around to 8000h
on the next read cycle. Figures 7 and 8 show the
proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first


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