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FM24C512-G データシート(PDF) 7 Page - Ramtron International Corporation |
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FM24C512-G データシート(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24C512 Rev. 1.0 Aug. 2006 Page 7 of 12 three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the device address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24C512 acknowledges the address, the bus master issues a Start condition. This simultaneously aborts the write operation and allows the read command to be issued with the device address LSB set to a 1. The operation is now a current address read. S A Slave Address 1 Data Byte 1 P By Master By FM24C512 Start Address Stop Acknowledge No Acknowledge Data A15 Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By FM24C512 Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge A15 Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By FM24C512 Start Address Stop No Acknowledge Data S A Slave Address 0 Address MSB A Start Address Acknowledge Address LSB A X A15 Figure 9. Selective (Random) Read Endurance A FRAM internally operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read and write access. The FRAM architecture is based on an array of rows and columns. Rows (A15-A6) are subdivided into 8 segments (A5-A3). Each access causes an endurance cycle for a row segment. In the FM24C512, there are 8 bytes per segment. Endurance can be optimized by ensuring frequently accessed data is located in different segments. Regardless, FRAM read and write endurance is effectively unlimited at the 1MHz two-wire speed. Even at 30 accesses per second to the same segment, 10 years time will pass before 10 billion endurance cycles occur. |
同様の部品番号 - FM24C512-G |
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同様の説明 - FM24C512-G |
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