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FM24C512-G データシート(PDF) 3 Page - Ramtron International Corporation

部品番号 FM24C512-G
部品情報  512Kb FRAM Serial Memory
Download  12 Pages
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM24C512-G データシート(HTML) 3 Page - Ramtron International Corporation

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FM24C512
Rev. 1.0
Aug. 2006
Page 3 of 12
Overview
The FM24C512 is a serial FRAM memory.
The
device has 65,536 locations with 8 data bits each and
is accessed using an industry standard two-wire
interface. Functional operation of the FRAM is
similar to serial EEPROMs. The major difference
between the FM24C512 and a serial EEPROM
relates to its superior write performance.
Memory Architecture
The FM24C512 is logically organized as two 32,768
x 8 bit memory arrays for a total of 65,536 locations.
The device should be treated as two banks, each bank
being selectable by the most significant address bit
A15. The MSB is located in the Slave Address byte
and can be considered a bank select bit. See Figure 4.
Data bits are shifted serially into and out of the
device. The 65,536 addresses are accessed using the
two-wire protocol, which includes a Slave Address
(to distinguish from other non-memory devices), and
a 16-bit address.
The memory is read or written at the speed of the
two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. By the time a new
bus transaction can be shifted into the part, a write
operation is complete. This is explained in more
detail in the interface section below.
Users can expect several obvious system benefits
from the FM24C512 due to its fast write cycle and
high
endurance
as
compared
with
EEPROM.
However there are less obvious benefits as well. For
example in a high noise environment, the fast-write
operation is less susceptible to corruption than an
EEPROM since the write cycle is completed quickly.
By contrast, an EEPROM requiring milliseconds to
write is vulnerable to noise during much of the cycle.
Note
that
the
FM24C512
contains
no
power
management circuits other than a simple internal
power-on reset. It is the user s responsibility to
ensure that VDD is maintained within data sheet
tolerances to prevent incorrect operation.
Two-wire Interface
The FM24C512 employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24C512 in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C512 is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the Electrical Specifications section.
Microcontroller
SDA
SCL
FM24C512
A1 A2
SDA
SCL
FM24C512
A1 A2
VDD
Rmin = 1.8 K?
Rmax = tR/Cbus
VDD
Figure 2. Typical System Configuration


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