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FM24CL16-S データシート(PDF) 10 Page - Ramtron International Corporation |
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FM24CL16-S データシート(HTML) 10 Page - Ramtron International Corporation |
10 / 13 page FM24CL16 Rev 3.3 Nov. 2005 Page 10 of 13 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing t SU:STA Start t R ` t F Stop Start t BUF t HIGH 1/fSCL t LOW t SP t SP Acknowledge t HD:DAT t SU:DAT t AA t DH SCL SDA Write Bus Timing t SU:STO Start Stop Start Acknowledge t AA t HD:DAT t HD:STA t SU:DAT SCL SDA Data Retention (VDD = 2.7V to 3.65V, 85°C) Parameter Min Units Notes Data Retention 45 Years |
同様の部品番号 - FM24CL16-S |
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同様の説明 - FM24CL16-S |
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