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SN74ACT574DWRE4 データシート(PDF) 1 Page - Texas Instruments |
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SN74ACT574DWRE4 データシート(HTML) 1 Page - Texas Instruments |
1 / 15 page SN54ACT574, SN74ACT574 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 9 ns at 5 V D Inputs Are TTL-Voltage Compatible description/ordering information These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ’ACT574 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74ACT574N SN74ACT574N SOIC DW Tube SN74ACT574DW ACT574 40 °Cto85°C SOIC – DW Tape and reel SN74ACT574DWR ACT574 –40 °C to 85°C SOP – NS Tape and reel SN74ACT574NSR ACT574 SSOP – DB Tape and reel SN74ACT574DBR AD574 TSSOP – PW Tape and reel SN74ACT574PWR AD574 CDIP – J Tube SNJ54ACT574J SNJ54ACT574J –55 °C to 125°C CFP – W Tube SNJ54ACT574W SNJ54ACT574W LCCC – FK Tube SNJ54ACT574FK SNJ54ACT574FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK SN54ACT574 ...J OR W PACKAGE SN74ACT574 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2Q 3Q 4Q 5Q 6Q 3D 4D 5D 6D 7D SN54ACT574 . . . FK PACKAGE (TOP VIEW) |
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同様の説明 - SN74ACT574DWRE4 |
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