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ML145026EP データシート(PDF) 3 Page - LANSDALE Semiconductor Inc. |
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ML145026EP データシート(HTML) 3 Page - LANSDALE Semiconductor Inc. |
3 / 19 page www.lansdale.com Page 3 of 19 Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 9 8 7 6 543 2 1 SEQUENCER CIRCUIT 1 2 3 4 5 15 14 13 12 A1 A2 A3 A4 A5 A6 A7 A8 A9 CONTROL LOGIC 9–BIT SHIFT REGISTER 9 Din 11 VT DATA EXTRACTOR Figure 3. ML145028 Decoder Block Diagram VDD = PIN 16 VSS = PIN 8 C1 C2 R2 R1 76 10 MAXIMUM RATINGS* (Voltages Referenced to VSS) Rating Symbol Value Unit VDD DC Supply Voltage – 0.5 to + 18 V VDD DC Supply Voltage – 0.5 to + 10 V Vin DC Input Voltage – 0.5 to VDD + 0.5 V Vout DC Output Voltage – 0.5 to VDD + 0.5 V Iin DC Input Current, per Pin ± 10 mA Iout DC Output Current, per Pin ± 10 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature – 65 to + 150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Func- tional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precau- tions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. |
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同様の説明 - ML145026EP |
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