LANSDALE Semiconductor, Inc.

ML145170

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Page 11 of 26

Figure 14. C Register Access and Format (8 Clock Cycles are Used)

*At this point, the new byte is transferred to the C register and stored. No other registers

are affected.

C7–POL:

Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts

PDout and interchanges the φR funtion with φV as depicted in Figure 17. Also see the phase

detector output pin description for more information. This bit is cleared low at power up.

C6–PDA/B:

Selects which phase/frequency detector is to be used. When set high, enables the output of

phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing φR

and

φV

R

and

φV) and phase/frequency detector A is disabled with PDout forced to the high–impedance

state. This bit is cleared low at power up.

C5–LDE:

Enables the lock detector output when set high. When the bit is cleared low, the LD output is

forced to a static low level. This bit is cleared low at power up.

C4–C2, OSC2–OSC0:

Reference output controls which determine the REFout characteristics as shown below. Upon

power up, the bits are initialized such that OSCin/8 is selected.

C4

C3

C2

0

0

0

DC (Static Low)

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

C1–fVE:

Enables the fV output when set high. When cleared low, the fV output is forced to a static low

level. The bit is cleared low upon power up.

C0–fRE:

Enables the fR output when set high. When cleared low, the fR output is forced to a static low

level. The bit is cleared low upon power up.

/4

to the static high state. When cleared low, phase/frequency detector B is enabled (

φ

Issue A