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MC145503P データシート(PDF) 4 Page - LANSDALE Semiconductor Inc.

部品番号 MC145503P
部品情報  PCM Codec-Filter Mono-Circuit
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メーカー  LANSDALE [LANSDALE Semiconductor Inc.]
ホームページ  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

MC145503P データシート(HTML) 4 Page - LANSDALE Semiconductor Inc.

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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Rating
Symbol
Value
Unit
DC Supply Voltage
VDD, VSS
– 0.5 to 13
V
Voltage, Any Pin to VSS
V
– 0.5 to VDD + 0.5
V
DC Drain Per Pin (Excluding VDD, VSS)
I
10
mA
Operating Temperature Range
TA
– 40 to + 85
°C
Storage Temperature Range
Tstg
– 85 to + 150
°C
RECOMMENDED OPERATING CONDITIONS (TA = – 40 to + 85°C)
Characteristic
Min
Typ
Max
Unit
DC Supply Voltage
Dual Supplies: VDD = – VSS, (VAG = VLS = 0 V)
Single Supply: VDD to VSS (VAG is an Output, VLS = VDD or VSS)
ML145502, ML145503, ML145505 (Using Internal 3.15 V Reference)
ML145502 Using Internal 2.5 V Reference
ML145502 Using Internal 3.78 V Reference
ML145502 Using External 1.5 V Reference, Referenced to VAG
4.75
8.5
7.0
9.5
4.75
5.0
6.3
12.6
12.6
12.6
12.6
V
Power Dissipation
CMOS Logic Mode (VDD to VSS = 10 V, VLS = VDD)
TTL Logic Mode (VDD = + 5 V, VSS = – 5 V, VLS = VAG = 0 V)
40
50
70
90
mW
Power Down Dissipation
0.1
1.0
mW
Frame Rate Transmit and Receive
7.5
8.0
8.5
kHz
Data Rate
ML145503
Must Use One of These Frequencies, Relative to MSI Frequency of 8 kHz
128
1536
1544
2048
2560
kHz
Data Rate for ML145502, ML145505
64
4096
kHz
Full Scale Analog Input and Output Level
ML145503, ML145505
ML145502 (V
RSI = V
)
ref = VSS
DD
RSI = VSS
RSI = VAG
ML145502 Using an External Reference V oltage Applied at Vref Pin
RSI = VDD
RSI = VSS
RSI = VAG
3.15
3.78
3.15
2.5
1.51 x Vref
1.26 x Vref
Vref
Vp
DIGITAL LEVELS (VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85°C)
Characteristic
Symbol
Min
Max
Unit
Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDI)
CMOS Mode (VLS = VDD, VSS is Digital Ground)
“0”
“1”
TTL Mode (VLS ≤ VDD – 4.0 V, VLS is Digital Ground)
“0”
“1”
VIL
VIH
VIL
VIH
0.7 x VDD
VLS + 2.0 V
0.3 x VDD
VLS + 0.8 V
V
Output Current for TDD (Transmit Digital Data)
CMOS Mode (VLS = VDD, VSS = 0 V and is Digital Ground)
(VDD = 5 V, Vout = 0.4 V)
(VDD = 10 V, Vout = 0.5 V)
(VDD = 5 V, Vout = 4.5 V)
(VDD = 10 V, Vout = 9.5 V)
TTL Mode (VLS ≤ VDD – 4.75 V, VLS = 0 V and is Digital Ground)
(VOL = 0.4 V)
(VOH = 2.4 V)
IOL
IOH
IOL
IOH
1.0
3.0
– 1.0
– 3.0
1.6
– 0.2
mA
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For
proper operation it is recommended that Vin
and Vout be constrained to the range VSS (Vin
or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., VSS, VDD,
VLS, or VAG).
www.lansdale.com
Page 4 of 26
Issue A


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