データシートサーチシステム |
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CD2481 データシート(PDF) 3 Page - Intel Corporation |
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CD2481 データシート(HTML) 3 Page - Intel Corporation |
3 / 222 page Datasheet 3 Programmable Four-Channel Communications Controller — CD2481 Contents 1.0 Features .........................................................................................................................9 1.1 Benefits ............................................................................................................... 11 1.2 CD2XXX Device Family Compatibility................................................................. 12 2.0 Conventions ...............................................................................................................13 2.1 Abbreviations....................................................................................................... 13 2.2 Acronyms ............................................................................................................14 3.0 Pin Information..........................................................................................................15 3.1 Pin Diagram — CD2481...................................................................................... 15 3.2 Pin Functions — CD2481.................................................................................... 16 3.3 Pin Descriptions .................................................................................................. 16 4.0 Register Summaries................................................................................................20 4.1 Memory Map ....................................................................................................... 20 4.1.1 Global Registers..................................................................................... 20 4.1.2 Option Registers..................................................................................... 21 4.1.3 Bit Rate and Clock Option Registers...................................................... 22 4.1.4 Channel Command and Status Registers .............................................. 22 4.1.5 Interrupt Registers..................................................................................22 4.1.6 DMA Registers ....................................................................................... 24 4.1.7 Timer Registers ...................................................................................... 25 4.2 Register Definitions ............................................................................................. 25 4.2.1 Global Registers..................................................................................... 25 4.2.2 Option Registers..................................................................................... 25 4.2.3 Bit Rate and Clock Option Registers...................................................... 29 4.2.4 Channel Command and Status Registers .............................................. 29 4.2.5 Interrupt Registers..................................................................................31 4.2.6 DMA Registers ....................................................................................... 34 4.2.7 Timer Registers ...................................................................................... 35 5.0 Functional Description...........................................................................................37 5.1 Host Interface ......................................................................................................37 5.1.1 Host Read and Write Cycles .................................................................. 37 5.1.2 Byte and Word Transfers ....................................................................... 39 5.2 Interrupts ............................................................................................................. 39 5.2.1 Contexts and Channels .......................................................................... 40 5.2.2 Interrupt Registers..................................................................................40 5.2.3 Groups and Types..................................................................................41 5.2.4 Hardware Signals and IACK Cycles ....................................................... 42 5.3 FIFO and Timer Operations ................................................................................ 44 5.3.1 Receive FIFO Operation ........................................................................ 44 5.3.2 Transmit FIFO Operation ....................................................................... 44 5.3.3 Timers .................................................................................................... 44 5.3.4 Timers in Synchronous Protocols........................................................... 45 5.3.5 Timers in Asynchronous Protocols......................................................... 45 5.3.6 Transmit Timer ....................................................................................... 45 |
同様の部品番号 - CD2481 |
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同様の説明 - CD2481 |
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