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SM34020APCM40 データシート(PDF) 6 Page - Texas Instruments |
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SM34020APCM40 データシート(HTML) 6 Page - Texas Instruments |
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6 / 89 page  SM34020APCM40 GRAPHICS SYSTEM PROCESSOR SGLS361 − JULY 2006 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME TYPE † DESCRIPTION Power VCC‡ I Nominal 5-V power supply. Five pins on QFP; nine pins on PGA. VSS‡ I Electrical ground. Nine pins on QFP; 17 pins on PGA. Emulation Control EMU0 − EMU 2 I Emulation 0 − 2 EMU3 O Emulation 3 Multiprocessor Interface GI I Bus grant input. External bus arbitration logic drives GI low to enable the SM34020APCM40 to gain access to the local-memory bus. The SM34020APCM40 must release the bus if GI is high so that another device can access the bus. Bus request and control. R1 and R0 indicate a request for use of the bus in a multiprocessor system; they are decoded as: R1, R0 O R1 R0 Bus Request Type L L High-priority bus request L H Bus-cycle termination H L Low-priority bus request H H No bus request pending A high-priority bus request provides for VRAM serial-data-register transfer cycles (midline or blanked), DRAM refresh (when 12 or more refresh cycles are pending), or a host-initiated access. The external arbitration logic should grant the request as soon as possible by asserting GI low. A low-priority bus request is used to provide for CPU-requested access and DRAM refresh (when less than 12 refresh cycles are pending). Bus-cycle termination status is provided so that the arbitration logic can determine that the device currently accessing the bus is completing an access, and other devices can compete for the next bus cycle. A no-bus-request-pending status is output when the currently active device does not require the bus on subsequent cycles. Video Interface CBLNK/VBLNK O Composite blanking / vertical blanking. CBLNK / VBLNK can be programmed to select one of two blanking functions: Composite blanking for blanking the display during both horizontal and vertical retrace periods in composite-sync-video mode Vertical blanking for blanking the display during vertical retrace in separate-sync-video mode Immediately following reset, CBLNK/VBLNK is configured as a CBLNK output. CSYNC/HBLNK I/O Composite synchronization / horizontal blanking. CSYNC/HBLNK can be programmed to select one of two functions: Composite sync (either input or output as set by a control bit in the DPYCTL register) in composite-sync-video mode: As an input, extracts HSYNC and VSYNC from externally-generated horizontal sync pulses As an output, CSYNC/HBLNK generates active-low composite-sync pulses from either externally generated HSYNC and VSYNC signals or signals generated by the SM34020APCM40’s on-chip video timers Horizontal blank (output only) for blanking the display during horizontal retrace in separate-sync-video mode Immediately following reset, CSYNC/HBLNK is configured as a CSYNC input. † I = input, O = output ‡ For proper SM34020APCM40 operation, all VCC and VSS pins must be connected externally. |
同様の部品番号 - SM34020APCM40 |
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同様の説明 - SM34020APCM40 |
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