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74ALVTH16373DLRG4 データシート(PDF) 1 Page - Texas Instruments |
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74ALVTH16373DLRG4 データシート(HTML) 1 Page - Texas Instruments |
1 / 19 page SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus ™ Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation D Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC) D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C D High Drive (–24/24 mA at 2.5-V and –32/64 mA at 3.3-V VCC) D Power Off Disables Outputs, Permitting Live Insertion D High-Impedance State During Power Up and Power Down Prevents Driver Conflict D Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating D Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method D Flow-Through Architecture Facilitates Printed Circuit Board Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package description The ’ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Copyright © 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. SN54ALVTH16373 . . . WD PACKAGE SN74ALVTH16373 ... DGG, DGV, OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE |
同様の部品番号 - 74ALVTH16373DLRG4 |
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同様の説明 - 74ALVTH16373DLRG4 |
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