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TMP1942XBG データシート(PDF) 10 Page - Toshiba Semiconductor

部品番号 TMP1942XBG
部品情報  32bit TX System RISC
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メーカー  TOSHIBA [Toshiba Semiconductor]
ホームページ  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP1942XBG データシート(HTML) 10 Page - Toshiba Semiconductor

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TX1942CY/CZ
2.2
Pin Usage Information
Table 2.2.1 lists the names and functions of the TMP1942’s input/output pins.
Table 2.2.1 Pin Names and Functions
Pin Name # of Pins
Type
Function
P00~P07
AD0~AD7
8
Input/output
Input/output
Port 0: Individually programmable as input or output
Address (Lower): Bits 0-7 of the address/data bus
P10~P17
AD8~AD15
A8~A15
8
Input/output
Input/output
Output
Port 1: Individually programmable as input or output
Address/Data (Upper): Bits 8-15 of the address/data bus
Address: Bits 8-15 of the address bus
P20~P27
A0~A7
A16~A23
8
Input/output
Output
Output
Port 2: Individually programmable as input or output
Address: Bits 0-7 of the address bus
Address: Bits 16-23 of the address bus
P30
RD
1
Output
Output
Port 30: Output-only
Read Strobe: Asserted during a read operation from an external memory device
P31
WR
1
Output
Output
Port 31: Output-only
Write Strobe: Asserted during a write operation on D0-D7
P32
HWR
1
Input/output
Output
Port 32: Programmable as input or output (with internal pull-up resister)
Higher Write Strobe: Asserted during a write operation on D8-D15
P33
WAIT
1
Input/output
Input
Port 33: Programmable as input or output (with internal pull-up resister)
Wait: Causes the CPU to suspend external bus activity
P34
BUSRQ
1
Input/output
Input
Port 34: Programmable as input or output (with internal pull-up resister)
Bus Request: Asserted by an external bus master to request bus mastership
P35
BUSAK
1
Input/output
Output
Port 35: Programmable as input or output (with internal pull-up resister)
Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to
BUSRQ
.
P36
R/W
1
Input/output
Output
Port 36: Programmable as input or output (with internal pull-up resister)
Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy
cycle, 0 = write cycle
P37
DSU
1
Input/output
Input
Port 37: Programmable as input or output (with internal pull-up resister)
This pin is used to select the operating mode during reset. The TMP1940CYAF enters
NORMAL mode when this pin is sampled high at the rising edge of RESET . This pin
should not be pulled down to a logic 0 during a reset sequence. The TMP1940FDBF,
which has an on-chip flash, uses this pin as an interface to the DSU tool. For details,
refer to Part 4, TMP1940FDBF.
P40
CS0
1
Input/output
Output
Port 40: Programmable as input or output (with internal pull-up resister)
Chip Select 0: Asserted low to enable external devices at programmed addresses
P41
CS1
1
Input/output
Output
Port 41: Programmable as input or output (with internal pull-up resister)
Chip Select 1: Asserted low to enable external devices at programmed addresses
P42
CS2
1
Input/output
Output
Port 42: Programmable as input or output (with internal pull-up resister)
Chip Select 2: Asserted low to enable external devices at programmed addresses
P43
CS3
1
Input/output
Output
Port 43: Programmable as input or output (with internal pull-up resister)
Chip Select 3: Asserted low to enable external devices at programmed addresses
P44
SCOUT
1
Input/output
Output
Port 44: Programmable as input or output
System Clock Output: Drives out a clock signal at the same frequency as the CPU
clock (high-speed or low-speed)
P50~P57
AN0~AN7
ADTRG
8
Input
Input
Input
Port 5: Input-only
Analog input: Input to the A/D converter
External start request for the A/D converter (multiplexed with P57)
P60~P67
AN8~AN15
KEY0-KEY7
1
Input/output
Input
Output
Port 6: Input-only
Analog input: Input to the A/D converter
Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable)
P90
DSU (DCLK)
KEY8
1
Input/output
Output
Input
Port 90: Programmable as input or output
DSU pin
Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable)
TMP1942CY/CZ-9


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