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TMPR4937 データシート(PDF) 5 Page - Toshiba Semiconductor |
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TMPR4937 データシート(HTML) 5 Page - Toshiba Semiconductor |
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5 / 552 page  Table of Contents i Table of Contents Handling precautions TMPR4937 1. Overview and Features ........................................................................................................................................... 1-1 1.1 Overview........................................................................................................................................................ 1-1 1.2 Features .......................................................................................................................................................... 1-1 1.2.1 Features of the TX49/H3 core.............................................................................................................. 1-2 1.2.2 Features of TX4937 peripheral functions ............................................................................................ 1-2 2. Configuration.......................................................................................................................................................... 2-1 2.1 TX4937 block diagram .................................................................................................................................. 2-1 3. Signals ............................................................................................................................................................. 3-1 3.1 Pin Signal Description ................................................................................................................................... 3-1 3.1.1 Signals Common to SDRAM and External Bus Interfaces.................................................................. 3-1 3.1.2 SDRAM Interface Signals ................................................................................................................... 3-2 3.1.3 External Interface Signals .................................................................................................................... 3-3 3.1.4 DMA Interface Signals ........................................................................................................................ 3-4 3.1.5 PCI Interface Signals ........................................................................................................................... 3-4 3.1.6 Serial I/O Interface Signals.................................................................................................................. 3-6 3.1.7 Timer Interface Signals........................................................................................................................ 3-6 3.1.8 Parallel I/O Interface Signals ............................................................................................................... 3-6 3.1.9 AC-link Interface Signals .................................................................................................................... 3-7 3.1.10 Interrupt Signals................................................................................................................................... 3-7 3.1.11 Extended EJTAG Interface Signals...................................................................................................... 3-8 3.1.12 Clock Signals ....................................................................................................................................... 3-8 3.1.13 Initialization Signal.............................................................................................................................. 3-9 3.1.14 Test Signals .......................................................................................................................................... 3-9 3.1.15 Power Supply Pins ............................................................................................................................... 3-9 3.2 Boot Configuration ...................................................................................................................................... 3-10 3.3 Pin multiplex................................................................................................................................................ 3-14 4. Address Mapping.................................................................................................................................................... 4-1 4.1 TX4937 Physical Address Map...................................................................................................................... 4-1 4.2 Register Map.................................................................................................................................................. 4-2 4.2.1 Addressing ........................................................................................................................................... 4-2 4.2.2 Ways to Access to Internal Registers ................................................................................................... 4-2 4.2.3 Register Map........................................................................................................................................ 4-3 5. Configuration Registers .......................................................................................................................................... 5-1 5.1 Detailed Description ...................................................................................................................................... 5-1 5.1.1 Detecting G-Bus Timeout .................................................................................................................... 5-1 5.2 Registers......................................................................................................................................................... 5-2 5.2.1 Chip Configuration Register (CCFG) 0xE000..................................................................................... 5-3 5.2.2 Chip Revision ID Register (REVID) 0xE008...................................................................................... 5-6 5.2.3 Pin Configuration Register (PCFG) 0xE010 ....................................................................................... 5-7 5.2.4 Timeout Error Access Address Register (TOEA) 0xE018 ................................................................ 5-10 5.2.5 Clock Control Register (CLKCTR) 0xE020...................................................................................... 5-11 5.2.6 G-Bus Arbiter Control Register (GARBC) 0xE030........................................................................... 5-13 5.2.7 Register Address Mapping Register (RAMP) 0xE048 ...................................................................... 5-14 6. Clocks ............................................................................................................................................................. 6-1 6.1 TX4937 Clock Signals ................................................................................................................................... 6-1 6.2 Power-Down Mode ........................................................................................................................................ 6-5 6.2.1 Halt Mode and Doze Mode.................................................................................................................. 6-5 |
同様の部品番号 - TMPR4937 |
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同様の説明 - TMPR4937 |
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