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データシートサーチシステム |
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データシートサーチシステム |
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TMPR4938XBG-300 データシート(PDF) 6 Page - Toshiba Semiconductor |
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TMPR4938XBG-300 データシート(HTML) 6 Page - Toshiba Semiconductor |
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6 / 716 page  Table of Contents ii 5.2.8 Jump Address Register (JMPADR) 0xE058 ...................................................................................... 5-16 6. Clocks ............................................................................................................................................................. 6-1 6.1 TX4938 Clock Signals ................................................................................................................................... 6-1 6.2 Power-Down Mode ........................................................................................................................................ 6-5 6.2.1 Halt Mode and Doze Mode.................................................................................................................. 6-5 6.2.2 Power Reduction for Peripheral Modules............................................................................................ 6-5 6.3 Power-On Sequence ....................................................................................................................................... 6-6 7. External Bus Controller .......................................................................................................................................... 7-1 7.1 Features .......................................................................................................................................................... 7-1 7.2 Block Diagram ............................................................................................................................................... 7-2 7.3 Detailed Explanation...................................................................................................................................... 7-3 7.3.1 External Bus Control Register ............................................................................................................. 7-3 7.3.2 Global/Boot-up Options....................................................................................................................... 7-4 7.3.3 Address Mapping................................................................................................................................. 7-5 7.3.4 External Address Output ...................................................................................................................... 7-6 7.3.5 Data Bus Size....................................................................................................................................... 7-7 7.3.6 Access Mode........................................................................................................................................ 7-9 7.3.7 Access Timing ................................................................................................................................... 7-13 7.3.8 Clock Options .................................................................................................................................... 7-19 7.3.9 ISA /ATA Mode ................................................................................................................................. 7-20 7.4 Register ........................................................................................................................................................ 7-24 7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7)...... 7-25 7.5 Timing Diagrams ......................................................................................................................................... 7-28 7.5.1 ACE* Signal ...................................................................................................................................... 7-29 7.5.2 Normal mode access (Single, 32-bit Bus).......................................................................................... 7-31 7.5.3 Normal mode access (Burst, 32-bit Bus) ........................................................................................... 7-35 7.5.4 Normal Mode Access (Single, 16-bit bus) .........................................................................................7-37 7.5.5 Normal Mode Access (Burst, 16-bit Bus) ..........................................................................................7-41 7.5.6 Normal Mode Access (Single, 8-bit Bus) ..........................................................................................7-43 7.5.7 Normal Mode Access (Burst, 8-bit Bus) ............................................................................................ 7-46 7.5.8 Page Mode Access (Burst, 32-bit Bus) .............................................................................................. 7-48 7.5.9 External ACK Mode Access (32-bit Bus) .......................................................................................... 7-50 7.5.10 READY Mode Access (32-bit Bus) ................................................................................................... 7-56 7.5.11 ISA IO Space Access ......................................................................................................................... 7-58 7.5.12 ATA/PIO Transfer Mode Access........................................................................................................ 7-60 7.6 Flash ROM, SRAM Usage Example ........................................................................................................... 7-62 8. DMA Controller...................................................................................................................................................... 8-1 8.1 Features .......................................................................................................................................................... 8-1 8.2 Block Diagram ............................................................................................................................................... 8-2 8.3 Detailed Explanation...................................................................................................................................... 8-4 8.3.1 Transfer Mode...................................................................................................................................... 8-4 8.3.2 On-chip Registers ................................................................................................................................ 8-5 8.3.3 External I/O DMA Transfer Mode ....................................................................................................... 8-5 8.3.4 Internal I/O DMA Transfer Mode ........................................................................................................ 8-8 8.3.5 Memory-Memory Copy Mode............................................................................................................. 8-9 8.3.6 Memory Fill Transfer Mode ................................................................................................................ 8-9 8.3.7 Single Address Transfer ....................................................................................................................... 8-9 8.3.8 Dual Address Transfer ....................................................................................................................... 8-12 8.3.9 DMA Transfer .................................................................................................................................... 8-17 8.3.10 Chain DMA Transfer ......................................................................................................................... 8-18 8.3.11 Dynamic Chain Operation ................................................................................................................. 8-20 8.3.12 Interrupts............................................................................................................................................ 8-21 8.3.13 Transfer Stall Detection Function ...................................................................................................... 8-21 8.3.14 Arbitration Among DMA Channels ................................................................................................... 8-22 |
同様の部品番号 - TMPR4938XBG-300 |
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同様の説明 - TMPR4938XBG-300 |
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