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TMPR4951B データシート(PDF) 8 Page - Toshiba Semiconductor |
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TMPR4951B データシート(HTML) 8 Page - Toshiba Semiconductor |
8 / 256 page Table of Contents iv 9.1.1 System Coordination ............................................................................................................................. 9-1 9.2 Reset Signal Description ................................................................................................................................ 9-2 9.2.1 Power-On Reset..................................................................................................................................... 9-2 9.2.2 Cold Reset ............................................................................................................................................. 9-3 9.3 User-Selectable Mode Configurations ........................................................................................................... 9-4 9.3.1 System Bus Interface Modes ................................................................................................................. 9-4 9.3.2 Clock Divisor for the System Bus ......................................................................................................... 9-4 9.3.3 System Endianness ................................................................................................................................ 9-4 9.3.4 Enabling and Disabling the Timer Interrupt .......................................................................................... 9-4 10. Clock Interface...................................................................................................................................................... 10-1 10.1 Signal Terminology...................................................................................................................................... 10-1 10.2 Basic System Clocks.................................................................................................................................... 10-2 10.2.1 MasterClock ........................................................................................................................................ 10-2 10.2.2 CPUCLK ............................................................................................................................................. 10-2 10.2.3 GBUSCLK .......................................................................................................................................... 10-2 10.2.4 CPUCLK-to-GBUSCLK Division ......................................................................................................10-3 10.2.5 Phase-Locked Loop (PLL) .................................................................................................................. 10-3 10.3 Connecting Clocks to a Phase-Locked System ............................................................................................ 10-4 11. TX4951B System Interface .................................................................................................................................. 11-1 11.1 Terminology................................................................................................................................................. 11-1 11.2 Explanation of System Interface of R5000 type protocol mode .................................................................. 11-1 11.2.1 Interface bus ........................................................................................................................................ 11-2 11.2.2 Address cycle and data cycle............................................................................................................... 11-2 11.2.3 Issue cycle ........................................................................................................................................... 11-3 11.2.4 Handshake signal................................................................................................................................. 11-4 11.2.5 System Interface Protocol of R5000 type............................................................................................ 11-4 11.2.6 Processor Requests and External Requests ......................................................................................... 11-6 11.2.7 Handling of Requests ........................................................................................................................ 11-10 11.2.8 Processor Request and External Request Protocol ............................................................................ 11-12 11.2.9 Data Transfer ..................................................................................................................................... 11-24 11.2.10 System Interface cycle time............................................................................................................... 11-25 11.2.11 System Interface Command and Data Identifiers .............................................................................. 11-26 11.2.12 System Interface Addresses ............................................................................................................... 11-31 11.2.13 Mode Register of System Interface (G2Sconfig) .............................................................................. 11-31 11.2.14 Data Error Detection ......................................................................................................................... 11-32 11.3 System Interface of R4300 type protocol mode......................................................................................... 11-33 11.3.1 System Interface Description of R4300 Type Protocol Mode ........................................................... 11-33 11.3.2 System Events ................................................................................................................................... 11-35 11.3.3 System Event Sequences and the SysAD Bus Protocol .................................................................... 11-35 11.3.4 System Interface Protocols ................................................................................................................ 11-38 11.3.5 Timing Summary............................................................................................................................... 11-40 11.3.6 Arbitration ......................................................................................................................................... 11-45 11.3.7 Issuing Commands ............................................................................................................................ 11-46 11.3.8 Processor Write Request.................................................................................................................... 11-46 11.3.9 Processor Read Request .................................................................................................................... 11-48 11.3.10 External Write Request...................................................................................................................... 11-48 11.3.11 External Read Response .................................................................................................................... 11-50 11.3.12 Flow Control ..................................................................................................................................... 11-52 11.3.13 Data Rate Control .............................................................................................................................. 11-53 11.3.14 Consecutive SysAD Bus Transactions .............................................................................................. 11-54 11.3.15 Starvation and Deadlock Avoidance. ................................................................................................. 11-56 11.3.16 Discarding and Re-Executing Read Command ................................................................................. 11-56 11.3.17 Multiple Drivers on the SysAD Bus.................................................................................................. 11-57 11.3.18 Signal Codes...................................................................................................................................... 11-58 11.3.19 Physical Addresses ............................................................................................................................ 11-60 11.3.20 Mode Register of System Interface (G2SConfig) ............................................................................. 11-60 |
同様の部品番号 - TMPR4951B |
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同様の説明 - TMPR4951B |
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