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TMP19A64C1DXBG データシート(PDF) 5 Page - Toshiba Semiconductor |
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TMP19A64C1DXBG データシート(HTML) 5 Page - Toshiba Semiconductor |
5 / 460 page TMP19A64C1D TMP19A64(rev1.1)1-3 (9) Serial bus interface : 1 channel • Either I 2C bus mode or clock synchronous mode can be selected (10) 10-bit A/D converter with (S/H) : 24 channels • Conversion speed: 54 clocks (7.85 μs@54 MHz) • Start by an internal timer trigger • Fixed channel/scan mode • Single/repeat mode • High-priority conversion mode • Timer monitor function (11) Watchdog timer : 1 channel (12) Interrupt source • CPU: 2 factors ............. software interrupt instruction • Internal: 50 factors....... The order of precedence can be set over 7 levels (except the watchdog timer interrupt). • External: 20 factors...... The order of precedence can be set over 7 levels (except the NMI interrupt). Because 8 factors are associated with KWUP, the number of interrupt factors is one. (13) 209 pins Input/output ports (14) Standby mode • 4 standby modes (IDLE, SLEEP, STOP and BACKUP) (15) Clock generator • On-chip PLL (multiplication by 4) • Clock gear function: The high-speed clock can be divided into 8/8, 7/8, 6/8, 5/8, 4/8, 2/8 or 1/8. • Sub-clock: SLOW, SLEEP and BACKUP modes (32.768 kHz) (16) Endian: Bi-endian (big-endian/little-endian) (17) Maximum operating frequency • 54 MHz (PLL multiplication) (18) Operating voltage range Core: 1.35 V to 1.65 V I/O: 1.65 V to 3.3 V ADC: 2.7 V to 3.3 V Backup block : 2.3 V to 3.3 V (under normal operating conditions) : 1.8 V to 3.3 V (in BACKUP mode) (19) Package • P-FBGA281 (13 mm × 13 mm, 0.65 mm pitch) |
同様の部品番号 - TMP19A64C1DXBG |
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同様の説明 - TMP19A64C1DXBG |
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