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M27W512-120N6TR データシート(PDF) 9 Page - STMicroelectronics |
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M27W512-120N6TR データシート(HTML) 9 Page - STMicroelectronics |
9 / 16 page 9/16 M27W512 PRESTO IIB Programming Algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 6.5 seconds. This can be achieved with STMicroelectronics M27W512 due to several design innovations described in the M27W512 datasheet to improve programming ef- ficiency and to provide adequate margin for reli- ability. Before starting the programming the internal MARGIN MODE circuit must be set in or- der to guarantee that each cell is programmed with enough margin. Then a sequence of 100 µs pro- gram pulses is applied to each byte until a correct verify occurs (see Figure 8). No overprogram puls- es are applied since the verify in MARGIN MODE at VCC much higher than 3.6V, provides the nec- essary margin. Program Inhibit Programming of multiple M27W512s in parallel with different data is also easily accomplished. Ex- cept for E, all like inputs including GVPP of the par- allel M27W512 may be common. A TTL low level pulse applied to a M27W512’s E input, with VPP at 12.75V, will program that M27W512. A high level E input inhibits the other M27W512s from being programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. The verify is accomplished with G at VIL. Data should be verified with tELQV after the falling edge of E. Figure 7. Programming and Verify Modes AC Waveforms AI00737 tVPLEL PROGRAM DATA IN A0-A15 E GVPP Q0-Q7 DATA OUT tAVEL tQVEL tVCHEL tVPHEL tEHQX tEHVPX tELEH tELQV tEHAX tEHQZ VERIFY VALID VCC Figure 8. Programming Flowchart AI00738C n= 0 Last Addr VERIFY E = 100 µs Pulse ++n =25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES 1st: VCC =5V 2nd: VCC = 2.7V YES NO YES NO YES NO SET MARGIN MODE RESET MARGIN MODE |
同様の部品番号 - M27W512-120N6TR |
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同様の説明 - M27W512-120N6TR |
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