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TL16PC564BLVI データシート(PDF) 5 Page - Texas Instruments |
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TL16PC564BLVI データシート(HTML) 5 Page - Texas Instruments |
5 / 34 page TL16PC564BLVI PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER SLLS627− SEPTEMBER 2004 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL INTER- † I/O DESCRIPTION NAME PZ NO. INTER- FACE† I/O DESCRIPTION HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 78 79 81 82 83 84 85 87 90 92 H I The 10-bit address bus addresses the attribute memory (bits 1 − 8) and addresses the internal UART as either PCMCIA I/O (bits 0 − 2) or as a standard COM port (bits 0 − 9). HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 77 76 75 100 99 98 96 95 H I/O The 8-bit bidirectional data bus transfers data to and from the attribute memory and the internal UART. INPACK 71 H O Input port acknowledge. INPACK is an active-low output signal that is asserted when the card responds to an I/O read cycle at the address on the HA bus. IORD 63 H I I/O read strobe. IORD is an active-low input signal activated to read data from the card I/O space. The REG signal and at least one of the card enable inputs (CE1, CE2) must also be active for the I/O transfer to take place. This signal has an internal pullup resistor. IOWR 64 H I I/O write strobe. IORW is an active-low input signal activated to write data to the card I/O space. The REG signal and at least one of the card enable inputs (CE1, CE2) must also be active for the I/O transfer to take place. This signal has an internal pullup resistor. IREQ 88 H O Interrupt request. IREQ is an active-low output signal asserted by the card to indicate to the host CPU that a card device requires host software service. This signal doubles as READY/BUSY during power-up initialization. IRQ 27 S O Interrupt request. This active-high IRQ to the subsystem indicates a host CPU write to attribute memory has occurred. NANDOUT 12 M O This is a production test output. OE 93 H I Output enable. OE is an active-low input signal used to gate memory read data from the card. This signal has an internal pullup resistor. OUT1 OUT2 37 44 U O Output 1 and output 2 are active-low signals. OUT1 and OUT2 are user-defined output terminals that are set to their active state by setting respective MCR bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high) state as a result of a reset, doing loop-mode operation, or by resetting bit 2 (OUT1) or bit 3 (OUT2) of the MCR. This signal has an open-drain outputs. RCLK 40 U I Receiver clock. RCLK is the 16 ×-baud-rate clock input for the receiver section of the UART. RD(DS) 29 S I Read enable or data strobe input. RD(DS) is the active-low read enable in the Intel mode and the active-low data strobe in the Zilog mode. REG 73 H I Attribute memory select. This active-low input signal is generated by the host CPU and accesses attribute memory (OE and WE active) and I/O space (IORD or IOWR active). PCMCIA common memory access is excluded. This signal has an internal pullup resistor and hysteresis on the input buffer. RESET 67 H I Reset. RESET is an active-high input that serves as the master reset for the device. RESET clears the UART, placing the card in an unconfigured state. This signal has an internal pullup resistor. † Host = H, Subsystem = S, UART = U, Miscellaneous = M |
同様の部品番号 - TL16PC564BLVI |
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同様の説明 - TL16PC564BLVI |
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