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ST6G3240 データシート(PDF) 6 Page - STMicroelectronics |
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ST6G3240 データシート(HTML) 6 Page - STMicroelectronics |
6 / 29 page Pin settings ST6G3240 6/29 CMD Command pin is a bidirectional line. The host and card drivers are operating in push-pull configuration. DAT0-3 All data lines are bi-directional lines. Host and card drivers operate in push-pull mode. CLK Clock is a host to card signal. CLK operates in push-pull mode. Feedback (return) clock is a feedback clock signal from level shifter to the host for controlling delays. CD Card detect with internal pull up resistor. Pin will be pulled to VCCA when it is in high state. IN1, IN2 Selection pins. When IN1 and IN2 are set to disabled state, all the data bus will be in high- impedance. When enabled, all the data bus will be working as a level translator between port A and port Bn (refer to the truth table for possible pin configuration). Pin Type Side Symbol Name and function D6 I/O B2 2DAT2 Data2 pin for B2-side E1 I/O A DAT2.h Data2 pin for A-side E2 O A CLK-f Feedback clock pin on A-side E3 O B2 2CLK Clock Output pin for B2-side E4 O B1 1CLK Clock Output pin for B1-side E5 I/O B1 1DAT3 Data3 pin for B1-side E6 I/O B2 2DAT3 Data3 pin for B2-side F1 I/O A DAT3.h Data3 pin for A-side F2 I A CLK.h Clock input pin for A-side F3 - A MS_Insert MS_Insert pin with 100 k Ω internal pull- up resistor on A-side F4 O B1 MS_InsertB1 MS_Insert pin on B1-side F5 - - GND Ground (0V) F6 - B2 VCCB2 B2-side power supply Table 3. Pin description (continued) |
同様の部品番号 - ST6G3240 |
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同様の説明 - ST6G3240 |
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