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AD5554BRS データシート(PDF) 9 Page - Analog Devices

部品番号 AD5554BRS
部品情報  Quad, Current-Output, Serial-Input 16-/14-Bit DACs
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD5554BRS データシート(HTML) 9 Page - Analog Devices

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AD5544/AD5554
Rev. A | Page 9 of 20
Table 6. AD55541 Control-Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register2 Function
Input Register2 Function
DAC Register
H
X
H
H
X3
No Effect
Latched
Latched
L
L
H
H
X
No Effect
Latched
Latched
L
↑+2
H
H
X
Shift-Register-Data Advanced
One Bit
Latched
Latched
L
H
H
H
X
No Effect
Latched
Latched
↑+2
L
H
H
X
No Effect
Selected DAC Updated with Current
Shift-Register Contents4
Latched
H
X
L
H
X
No Effect
Latched
Transparent
H
X
H
H
X
No Effect
Latched
Latched
H
X
+
H
X
No Effect
Latched
Latched
H
X
H
L
0
No Effect
Latched Data = 0000H
Latched Data = 0000H
H
X
H
L
H
No Effect
Latched Data = 2000H
Latched Data = 2000H
1 For the AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.
2
↑+ positive logic transition.
3 X = don’t care.
4 At power on both the input register and the DAC register are loaded with all zeros.
Table 7. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1 Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D15 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC registers.
Table 8. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1 Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point an
internally generated load strobe transfers the serial register data contents (Bits D13 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0.
Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be
tied logic low to disable the DAC registers.
Table 9. Address Decode
A1
A0
DAC Decoded
0
0
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D


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