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ST24C08M3TR データシート(PDF) 9 Page - STMicroelectronics |
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ST24C08M3TR データシート(HTML) 9 Page - STMicroelectronics |
9 / 16 page AI01121B 3FFh b7 b2 XX 300h Block 3 Block 0 Protect Flag Enable = 0 Disable = 1 Page pointer b4 0 Figure 7. Memory Protection of data, which are each acknowledged by the mem- ory. After each byte is transfered, the internal byte address counter (4 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory pro- gram cycle. All inputs are disabled until the comple- tion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory discon- nects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be re- duced by an ACK polling sequence issued by the master. WRITE Cycle in Progress AI01099B Next Operation is Addressing the Memory START Condition DEVICE SELECT with RW = 0 ACK Returned YES NO YES NO ReSTART STOP Proceed WRITE Operation Proceed Random Address READ Operation Send Byte Address First byte of instruction with RW = 0 already decoded by ST24xxx Figure 8. Write Cycle Polling using ACK 9/16 ST24/25C08, ST24/25W08 |
同様の部品番号 - ST24C08M3TR |
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同様の説明 - ST24C08M3TR |
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