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ST5088D データシート(PDF) 8 Page - STMicroelectronics

部品番号 ST5088D
部品情報  PROGRAMMABLE AUDIO FRONT END FOR DIGITAL PHONES AND ISDN TERMINALS
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST5088D データシート(HTML) 8 Page - STMicroelectronics

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switchable anti-larsen for loudspeaker to handset
microphone feedback is implemented. A 12dB
depth gain control on both transmit and receive
path is provided to keep constant the loop gain.
On the transmit path the 12dB gain control is pro-
vided starting from the CR5 transmit gain defini-
tion; at the same time, on the receive path the
12dB gain control is provided starting from CR6
receive gain definition.
DIGITAL ANTICLIPPING SYSTEM (D.A.S.)
An automatic anticlipping system is necessary to
avoid distortion on LS+/LS- when the output
swing approaches the supply rails. (LS GAIN >>
+9dB).
The digital anticlipping system calculates equiva-
lent input signal on DR pin and compares it with a
selectable anticlipping threshold. The D.A.S. is
then able to reduce the overall gain in order to
avoid or limit the distortion.
Four different thresholds are programmable via
register:
-15dBm0
D < 1%
For safe margin
-13dBm0
D = 1%
For normal operation
-9dBm0
D
≥ 1%
For noisy ambient (*)
-7dBm0
D >> 1%
For very noisy ambient (*)
(*) When environment is noisy, power output
might be more important than 1% distortion.
Gain reduction of the D.A.S. (Anticlipping Attack)
has a fixed speed of 8KHz.
Gain recovery or increase (Anticlipping Release)
has 4 programmable speeds of 4Hz, 8Hz, 31Hz
and 62Hz.
TAPE RECORDER OUTPUT (TRO)
This section provides a combination of Tx and Rx
Analog Signals to an external user like a re-
cordering machine. The output levels relative to a
signal of 0dBm0 on channel Dx and DR are:
Rx TRO = 0.245VRMS (for 0dBm0 on DR)
Tx TRO = 0.246VRMS (for 0dBm0 on DX)
The single ended Op Amp is able to drive an ex-
ternal load as low as 600
Ω.
ALTERNATE TONE CONTROL (AT)
This section allows to simplify the microprocessor
control of ringer operation. When pin AT is put ex-
ternally at high impedance state (or left open) the
control of ring frequency emission is totally
through a microprocessor, which updates in real
time the contents of various registers.
When pin AT is forced at GND or Vcc the ring
generator emits respectively the frequencies f2
(GND) and f1 (Vcc), previously defined through
registers CR9 (f2) and CR8(f1). This operative
mode requires only start-up intervention of the mi-
croprocessor.
Digital and Control Interface:
PIAFE provides a choice of either of two types of
Digital Interface for both control data and PCM.
For compatibility with systems which use time slot
oriented PCM busses with a separate Control In-
terface, as used on COMBO I/II families of de-
vices, PIAFE functions are described in next sec-
tion.
Alternatively, for systems in which PCM and con-
trol data are multiplexed together using GCI inter-
face scheme, PIAFE functions are described in
the section following the next one.
PIAFE will automatically switch to one of these
two types of interface by sensing the MS pin.
Due to Line Transceiver clock recovery circuitry, a
low jitter may be provided on FS and MCLK
clocks. FS and MCLK must be always in phase.
For ST5421S Transceiver, as an example,
maximun value of jitter amplitude is a step of 65
ns at each GCI frame (125
µs). So, the maximum
jitter amplitude is 130 ns pk-pk.
COMBO I/II mode.
Digital Interface (Fig. 1)
FS Frame Sync input determines the beginning of
frame. It may have any duration from a single cy-
cle of MCLK to a squarewave. Two different rela-
tionships may be established between the Frame
Sync input and the first time slot of frame by set-
ting bit 3 in register CR0. Non delayed data mode
is similar to long frame timing on ETC5057/
TS5070 series of
devices (COMBO I
and
COMBO II respectively): first time slot begins
nominally coincident with the rising edge of FS.
Alternative is to use delayed data mode, which is
similar to short frame sync timing on COMBO I or
COMBO II, in which FS input must be high at least
a half cycle of MCLK earlier the frame beginning.
A time slot assignment circuit on chip may be
used with both timing modes, allowing connection
to one of the two B1 and B2 voice data channels.
Two data formats are available: in Format 1, time
slot B1 corresponds to the 8 MCLK cycles follow-
ing immediately the rising edge of FS, while time
slot B2 corresponds to the 8 MCLK cycles follow-
ing immediately time slot B1.
In Format 2, time slot B1 is identical to Format 1.
Time slot B2 appears two bit slots after time slot
B1. This two bits space is left available for inser-
tion of the D channel data.
Data format is selected by bit FF (2) in register
CR0. Time slot B1 or B2 is selected by bit T0 (0)
in Control Register CR1.
Bit EN (2) in control register CR1 enables or dis-
ables the voice data transfer on DX and DR as
appropriate. During the assigned time slot, DX
ST5088
8/33


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