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ST52T301 データシート(PDF) 6 Page - STMicroelectronics |
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ST52T301 データシート(HTML) 6 Page - STMicroelectronics |
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6 / 100 page  2 INTERNAL ARCHITECTURE ST52x301 is made up by the following blocks and peripherals: Control Unit Fuzzy Core ALU EPROM Clock Oscillator Analog Multiplexer and A/D Converter Prescaler Timer Bandgap Triac / PWM Driver Digital I/O port Serial Communication Interface ST52x301 Operating Modes ST52x301 works in two modes, Programming and Working Modes, depending on the control signals level RESET, TEST and MODE. The Operating modes are selected by setting the control signal level as specified in the Control Signals Setting table. 2.1 CONTROL UNIT The Control Unit (CU) manages: Registers File, Input Registers, Configuration Registers, ALU, Accumulator and Multiplexer inputs. Moreover the CU drives the Fuzzy Core and the peripherals (Triac/PWM Driver and Timer). The CU reads the stored instructions on the EPROM (Fetch) and decodifies them. If the instructions are arithmetic or logic, the CU runs them directly, sending the control signals to the related blocks. If there is a STOP instruction, the CU transfers the control to the Fuzzy Core. The Fuzzy Core (FC) will read the next instruction (that must be a fuzzy instruction)from the EPROM. The FC mantains the control of the program until the next STOP instruction. Then the FC transfers the control to the CU. These characteristicsallow to mix fuzzy algorithms with mathematical and logic instructions. Figure 2.1 shows a flow-chart reasuming the logic behaviour of the instructions management. Control Sign al Programming Reset Working RESET 00 1 TEST 00 0 MODE 10 0 Table 2.1. Control Signals setting CU Reads fromthe EPROM and Decodifies the instruction CU executes instruction Fuzzy Core Reads fromthe EPROM and Decodifies the instruction STOP? STOP? No No Fuzzy Core executes instruction Yes Yes Figure 2.1. Computation Algorithm Flow Chart 6/99 ST52T301/E301 |
同様の部品番号 - ST52T301 |
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同様の説明 - ST52T301 |
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