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SM320DM642-EP データシート(PDF) 3 Page - Texas Instruments |
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SM320DM642-EP データシート(HTML) 3 Page - Texas Instruments |
3 / 170 page www.ti.com 1.2.1 Device Compatibility SM320DM642-EP Video/Imaging Fixed Point Digital Signal Processor SGUS058B – JUNE 2007 – REVISED JANUARY 2008 The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins that can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all eight serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output.For more details on the VIC port, see the TMS320C64x™ DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception.For more details on the EMAC, see the TMS320C6000™ DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000™ DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The I2C0 port on the DM642 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The DM642 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution. The DM642 device is a code-compatible member of the C6000 DSP platform. The C64x DSP generation of devices has a diverse and powerful set of peripherals. For more detailed information on the device compatibility and similarities/differences among the DM642 and other C64x devices, see the TMS320DM642 Technical Overview (literature number SPRU615). Submit Documentation Feedback SM320DM642 Video/Imaging Fixed-Point Digital Signal Processor 3 |
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同様の説明 - SM320DM642-EP |
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