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M41T00S データシート(PDF) 11 Page - STMicroelectronics |
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M41T00S データシート(HTML) 11 Page - STMicroelectronics |
11 / 26 page M41T00S Operation 11/26 2.4 Data retention mode With valid VCC applied, the M41T00S can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At this time the clock registers will be maintained by the attached battery supply. On power-up, when VCC returns to a nominal value, write protection continues for tREC. For a further, more detailed review of lifetime calculations, please see Application Note AN1012. Figure 9. WRITE mode sequence AI00591 BUS ACTIVITY: S P SDA LINE BUS ACTIVITY: MASTER DATA n DATA n+1 DATA n+X WORD ADDRESS (An) SLAVE ADDRESS |
同様の部品番号 - M41T00S |
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同様の説明 - M41T00S |
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