データシートサーチシステム |
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74AC10MTR データシート(PDF) 1 Page - STMicroelectronics |
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74AC10MTR データシート(HTML) 1 Page - STMicroelectronics |
1 / 8 page 1/8 April 2001 s HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74AC10 TRIPLE 3-INPUT NAND GATE PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74AC10B SOP 74AC10M 74AC10MTR TSSOP 74AC10TTR TSSOP DIP SOP |
同様の部品番号 - 74AC10MTR |
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同様の説明 - 74AC10MTR |
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