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M40ZTHSMH6E データシート(PDF) 8 Page - STMicroelectronics

部品番号 M40ZTHSMH6E
部品情報  5V or 3V NVRAM supervisor for up to two LPSRAMs
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M40ZTHSMH6E データシート(HTML) 8 Page - STMicroelectronics

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Operation
M40Z111, M40Z111W
8/21
2
Operation
The M40Z111/W, as shown in Figure 3 on page 7, can control up to two standard low-power
SRAMs. These SRAMs must be configured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are configured like this, however many fast
SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON)
output pin follows the chip enable (E) input pin with timing shown in Table 2 on page 10. An
internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V
(IOUT1).
When VCC degrades during a power failure, ECON is forced inactive independent of E. In this
situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance
threshold (VPFD). The power fail detection value associated with VPFD is selected by the
THS pin and is shown in Table 6 on page 14.
Note:
Note: The THS pin must be connected to either VSS or VOUT.
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time tWP, ECON is unconditionally driven high, write protecting the SRAM.
A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user
can be assured the memory will be write protected provided the VCC fall time exceeds tF.
As VCC continues to degrade, the internal switch disconnects VCC and connects the internal
battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery
provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 6 on
page 14). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output
ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD,
independent of the E input, to allow for processor stabilization (see Figure 5 on page 9).
2.1
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and
SRAMs to be “Don't Care” once VCC falls below VPFD (min). The SRAM should also
guarantee data retention down to VCC = 2.0V. The chip enable access time must be
sufficient to meet the system needs with the chip enable propagation delays included. If the
SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data
retention lifetime is a critical parameter for the system, it is important to review the data
retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
Manufacturers generally specify a typical condition for room temperature along with a worst
case condition (generally at elevated temperatures). The system level requirements will
determine the choice of which value to use. The data retention current value of the SRAMs
can then be added to the ICCDR value of the M40Z111/W to determine the total current
requirements for data retention.


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