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LC4064ZE5MN48I データシート(PDF) 3 Page - Lattice Semiconductor |
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LC4064ZE5MN48I データシート(HTML) 3 Page - Lattice Semiconductor |
3 / 54 page Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 3 The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards com- patible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con- nected to a VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces. Architecture There are a total of two GLBs in the ispMACH 4032ZE, increasing to 16 GLBs in the ispMACH 4256ZE. Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the asso- ciated I/O cells in the I/O block. Generic Logic Block The ispMACH 4000ZE GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou- pled from macrocells through the ORP. Figure 2 illustrates the GLB. Figure 2. Generic Logic Block AND Array The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con- nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array. 36 Inputs from GRP To GRP To Product Term Output Enable Sharing. Also, To Input Enable of Power Guard on I/Os in the block. 1+OE Clock Generator 1+OE 1+OE 1+OE 1+OE 1+OE 1+OE 1+OE |
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