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LC4256ZE5MN100C データシート(PDF) 8 Page - Lattice Semiconductor |
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LC4256ZE5MN100C データシート(HTML) 8 Page - Lattice Semiconductor |
8 / 54 page Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 8 Output Routing Pool (ORP) The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block. This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This allows the OE product term to follow the macrocell output as it is switched between I/O cells. The enhanced ORP of the ispMACH 4000ZE family consists of the following elements: • Output Routing Multiplexers • OE Routing Multiplexers Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each ORP has as many ORP slices as there are I/O cells in the corresponding I/O block. Figure 7. ORP Slice Output Routing Multiplexers The details of connections between the macrocells and the I/O cells vary across devices and within a device dependent on the maximum number of I/Os available. Tables 5-7 provide the connection details. Table 5. GLB/MC/ORP Combinations for ispMACH 4256ZE GLB/MC ORP Mux Input Macrocells [GLB] [MC 0] M0, M1, M2, M3, M4, M5, M6, M7 [GLB] [MC 1] M2, M3, M4, M5, M6, M7, M8, M9 [GLB] [MC 2] M4, M5, M6, M7, M8, M9, M10, M11 [GLB] [MC 3] M6, M7, M8, M9, M10, M11, M12, M13 [GLB] [MC 4] M8, M9, M10, M11, M12, M13, M14, M15 [GLB] [MC 5] M10, M11, M12, M13, M14, M15, M0, M1 [GLB] [MC 6] M12, M13, M14, M15, M0, M1, M2, M3 [GLB] [MC 7] M14, M15, M0, M1, M2, M3, M4, M5 Output Routing Multiplexer OE Routing Multiplexer From Macrocell From PTOE To I/O Cell To I/O Cell OE |
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同様の説明 - LC4256ZE5MN100C |
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