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LS110GXS-1CF269I データシート(PDF) 7 Page - Lattice Semiconductor |
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LS110GXS-1CF269I データシート(HTML) 7 Page - Lattice Semiconductor |
7 / 23 page Lattice Semiconductor XPIO 110GXS Data Sheet 7 Mode 2: Synchronous line loopback with clock clean-up. Driving LB_P622_Enb low enables line loopback mode. In order to make this loopback mode SONET/SDH compliant the CK622OUT_P/N must be connected to a VCXO-powered PLL chip (e.g. MAX3670), and CK622OUT_SEL pulled/driven high. The output of the PLL provides a low jitter reference clock that is in phase with the data presented at the LVDS parallel outputs. This reference clock is connected to REF_CK_P/N. As in Mode 1 a separate reference clock is input to RX_REF_CK_P/N to drive the CDR logic. Data on the TX_D_P/N and RX_D_P/N pins are now synchronous, and the data repeated on TX_D_P/N meets SONET/SDH line loopback application requirements. Figure 4. Line Loopback Mode 2 Block Diagram Reference Clocks There are two AC coupled reference clock input pairs, REF_CK_P/N, and RX_REF_CK_P/N. The CDR block is driven by either REF_CK_P/N or RX_REF_CK_P/N. The CMU block is only driven by REF_CK_P/N. The reference clock input frequency for REF_CK_P/N can be either 1/16 th (622MHz) or 1/64th (155MHz) the transmitter/receiver data rate. Likewise, RX_REF_CK_P/N can be 1/16 th or 1/64th the 10Gbps receiver rate. RX_REF_CK_P/N and REF_CK_P/N are configured in tandem to 1/16 th or 1/64th by REF_CK_SEL. They cannot be configured indepen- dently. AC coupling for all reference clocks is recommended. RX LVDS Data TX LVDS Data 10G RX 10G TX 1 0 1 0 LB_LVDS_ENb=1 RX_D_LV[0..15] TX_D_LV[0..15] TX_CL_LV_P/N Deserializer Serializer TX_D_P RX_D_P TX_D_N RX_D_N RX_CK_LV_P/N Parallel Loopback CMU REF_CK_P/N BIST_ENb=0 BIST_LB_SC0=0 BIST_LB_SC1=1 LVDS Loopback Mode 1 LB_P622_ENb=0 External Low Jitter PLL (e.g. MAX 3670) CK622_OUT_PN CK622OUT_SEL = 1 To REF_CK_P/N Low Jitter Clock Synchronous to REF_CK_P/N Reference PLL |
同様の部品番号 - LS110GXS-1CF269I |
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同様の説明 - LS110GXS-1CF269I |
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