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FDD8870 データシート(PDF) 8 Page - Fairchild Semiconductor |
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FDD8870 データシート(HTML) 8 Page - Fairchild Semiconductor |
8 / 11 page ©2008 Fairchild Semiconductor Corporation FDD8870 / FDU8870 Rev. C2 PSPICE Electrical Model .SUBCKT FDD8870 2 1 3 ; rev July 2003 Ca 12 8 4.2e-9 Cb 15 14 4.2e-9 Cin 6 8 4.7e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 32.7 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2e-9 RLgate 1 9 50 RLdrain 2 5 10 RLsource 3 7 20 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.57e-3 Rgate 9 20 2.1 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 1.2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=1.3E-11 IKF=10 N=1.01 RS=1.8e-3 TRS1=8e-4 TRS2=2e-7 + CJO=2e-9 M=0.57 TT=1e-10 XTI=0.9) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.6e-9 IS=1e-30 N=10 M=0.38) .MODEL MmedMOD NMOS (VTO=1.76 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25) .MODEL MstroMOD NMOS (VTO=2.2 KP=650 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=1.47 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7) .MODEL RdrainMOD RES (TC1=2e-4 TC2=8e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=8e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2e-3 TC2=-9.5e-6) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 18 22 + - 6 8 + - 5 51 19 8 + - 17 18 6 8 + - 5 8 + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 19 22 12 13 15 S1A S1B S2A S2B CA CB EGS EDS 14 8 13 8 14 13 MWEAK EBREAK DBODY RSOURCE SOURCE 11 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 16 21 8 MMED MSTRO DRAIN 2 LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 10 5 51 50 RSLC2 1 GATE RGATE EVTEMP 9 ESG LGATE RLGATE 20 + - + - + - 6 |
同様の部品番号 - FDD8870_08 |
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同様の説明 - FDD8870_08 |
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