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MC13224VR2 データシート(PDF) 11 Page - Freescale Semiconductor, Inc

部品番号 MC13224VR2
部品情報  Advanced ZigBee?? Compliant Platform-in-Package (PiP) for the 2.4 GHz IEEE짰 802.15.4 Standard
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC13224VR2 データシート(HTML) 11 Page - Freescale Semiconductor, Inc

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MC13224V Product Preview, Rev. 1.7
Freescale Semiconductor
11
Figure 4. Optional Buck Regulator
2.6.4
Battery Detect
An optional feature of the ADC module is battery voltage detect. Programmable thresholds are provided
for an ADC analog sample channel to monitor the battery high voltage and battery low voltage. This
feature can be used as a trigger to provide low battery indication, protection for data that may be lost due
to end-of-life for the battery, monitoring charging, and controlling buck regulator operation.
2.7
IEEE 802.15.4 Acceleration Hardware
The MC13224V provides acceleration hardware for IEEE 802.15.4 applications and this hardware
includes 802.15.4 MAC acceleration and AES encryption/decryption.
2.7.1
802.15.4 MAC Accelerator (MACA) Overview
The MC13224V contains a hardware block that provides a low-level MAC and PHY link controller, which
together with software running on the ARM core, implements the baseband protocols and other low-level
link routine control and link control. Components of the MACA include a sequencer/controller (with
timers), TX and RX packet buffers, DMA block, frame check sequence (FCS) generator/checker, and
control registers. Figure 5 shows a MACA simplified block diagram.
As part of the 802.15.4 protocol, packets are generated and transmitted, packets are received and verified,
and channel energy is measured via a clear channel assessment (CCA). Also, combinations or sequences
of events are required as part of the protocol such as an ACK response following a received packet. The
MACA facilitates these activities via control of the transceiver and off loads the functions from the CPU.
A dedicated DMA function moves data between the MACA buffers and RAM on a cycle steal basis and
does not require intervention from the CPU.
The MACA is responsible for construction of packets for TX including FCS, and for parsing the received
packets. The MACA will also handle ACKs and TxPoll sequences independent of the ARM processor.
During TX the MACA will construct the entire packet. This includes preamble and SFD (start of frame
LREG_BK_FB
VDD
L2
100uH
C2
10uF
COIL_BK
VBATT
MC13224V
VBATT
COIL_BK
LREG_BK_FB
VDD
NC
MC13224V
Normal Operation
Buck Regulator


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