R1LV3216R Series

Preliminary

REJ03C0367-0001, Rev.0.01, 2008.03.24

Page 9 of 16

Write Cycle

R1LV3216R**-5S

(Note 0)

R1LV3216R**-7S

Parameter

Symbol

Min.

Max.

Min.

Max.

Unit

Note

Write cycle time

55

-

70

-

ns

Address valid to end of write

50

-

65

-

ns

Chip select to end of write

50

-

65

-

ns

5

Write pulse width

40

-

55

-

ns

4

LB#, UB# valid to end of write

50

-

65

-

ns

Address setup time

0

-

0

-

ns

6

Write recovery time

0

-

0

-

ns

7

Data to write time overlap

25

-

35

-

ns

Data hold from write time

0

-

0

-

ns

Output enable from end of write

5

-

5

-

ns

2

Output disable to output in high-Z

0

20

0

25

ns

1,2

Write to output in high-Z

0

20

0

25

ns

1,2

Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on

customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts.

are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

from device to device.

4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#

going low or UB# going low .

A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#