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TS4851 データシート(PDF) 3 Page - STMicroelectronics

部品番号 TS4851
部品情報  MONO 1 W SPEAKER AND STEREO 160 mW HEADSET BTL DRIVERS WITH DIGITAL VOLUME CONTROL
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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SPI Bus Interface
TS4851
3/28
2 SPI Bus Interface
2.1 Description of SPI operation
The serial data bits are organized into a field containing 8 bits of data as shown in Table 3. The DATA 0 to
DATA 2 bits determine the output mode of the TS4851 as shown in Table 2. The DATA 3 to DATA 7 bits
determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to
the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the
CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to
complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK
and DATA transitions will be ignored after the height rising clock edge has occurred. For any data
sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits
will be disregarded.
Table 2.
Pin description
Pin
Functional Description
DATA
This is the serial data input pin.
CLK
This is the clock input pin.
ENB
This is the SPI enable pin active at high level.
Table 3.
Bit allocation
DATA
MODES
LSB
DATA 0
Mode 1
DATA 1
Mode 2
DATA 2
Mode 3
DATA 3
gain 1
DATA 4
gain 2
DATA 5
gain 3
DATA 6
gain 4
MSB
DATA 7
gain 5
Table 4.
Output mode selection: G from -34.5dB to +12dB (by steps of 1.5dB)
Output
Mode #
DATA 2
DATA 1
DATA 0
SPKERout1
1)
SD = Shutdown Mode, P = Phone in Input, R = Rin input and L = Lin input
Rout
Lout
0
0
0
0
SD
SD
SD
1
0
0
1
6dBxP
SD
SD
2
0
1
0
SD
0dBxP
0dBxP
30
1
1
Gx(R+L)
SD
SD
41
0
0
SD
GxR
GxL
51
0
1
Gx(R+L)
+6dBxP
SD
SD
6
1
1
0
SD
GxR+0dBxP
GxL+0dBxP
7
1
1
1
6dBxP
GxR+0dBxP
GxL+0dBxP


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