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MC15XS3400 データシート(PDF) 33 Page - Freescale Semiconductor, Inc |
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MC15XS3400 データシート(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 49 page  Analog Integrated Circuit Device Data Freescale Semiconductor 33 15XS3400 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS SERIAL INPUT COMMUNICATION SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bits D14:D13. The next three bits, D12:D10, are used to select the command register. The remaining nine bits, D8:D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 15XS3400 has defined registers, which are used to configure the device and to control the state of the outputs. Table 10 summarizes the SI registers. Table 9. SI Message Bit Assignment Bit Sig SI Msg Bit Message Bit Description MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D14 :D13 Register address bits used in some cases for output selection ( Table 12). D12 :D10 Register address bits. D9 Not used (set to logic [0]). LSB D8:D0 Used to configure the inputs, outputs, and the device protection features and SO status content. Table 10. Serial Input Address and Configuration Bit Map SI Register SI Data D15 D1 4 D13 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 STATR_s WDI N X X 0 0 0 0 0 0 0 0 SOA4 SOA3 SOA2 SOA1 SOA0 PWMR_s WDI N A1 A0 0 0 1 0 28W_s ON_s PWM6_s PWM5_s PWM4_s PWM3_s PWM2_s PWM1_s PWM0_s CONFR0_ s WDI N A1 A0 0 1 0 0 0 0 0 DIR_dis_s SR1_s SR0_s DELAY2_s DELAY1_s DELAY0_s CONFR1_ s WDI N A1 A0 0 1 1 0 0 0 Retry_ unlimited_s Retry_dis_s OS_dis_s OLON_dis_s OLOFF_dis_ s OLLED_en _s CSNS_ratio _s OCR_s WDI N A1 A0 1 0 0 0 Xenon_ s BC1_s BC0_s OC1_s OC0_s OCHI_s OCLO1_s OCLCO0_s OC_mode_ s GCR WDI N 0 0 1 0 1 0 VDD_F AIL_en PWM_en CLOCK_sel TEMP_en CSNS_en CSNS1 CSNS0 X OV_dis CALR WDI N 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 Register state after RST=0 or VDD(FAIL) or VSUPPLY(P OR) condition 0 0 0 X X X 0 0 0 0 0 0 0 0 0 0 x=Don’t care. s=Output selection with the bits A1A0 as defined in Table 11. |
同様の部品番号 - MC15XS3400 |
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同様の説明 - MC15XS3400 |
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