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ADXL345BCCZ-RL1 データシート(PDF) 10 Page - Analog Devices |
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ADXL345BCCZ-RL1 データシート(HTML) 10 Page - Analog Devices |
10 / 24 page ADXL345 Preliminary Technical Data Rev. PrA | Page 10 of 24 CS SCLK SDI SDO R/W MB A[5] A[4] A[3] A[2] A[1] A[0] D[6] D[7] D[5] D[4] D[3] D[2] D[1] D[0] tDELAY tSCLK tS tM tQUIET tSETUP tHOLD tSDO CS SCLK SDI SDO R/W MB A[5] A[4] A[3] A[2] A[1] A[0] D[6] D[7] D[5] D[4] D[3] D[2] D[1] D[0] tDELAY tSCLK tS tM tQUIET tSETUP tHOLD tSDO Figure 7. SPI 4-wire Write Timing Diagram Table 7. SPI Timing Specifications (TA = 25°C, VS = 2.5V, VDD I/O = 1.8V) Parameter Limit Unit Description fSCLK 5 MHz max SPI clock frequency tSCLK 200 ns min 1/(SPI clock frequency) Mark/space ratio for the SCLK input is 40/60 to 60/40 tDELAY 200 ns min falling edge to SCLK falling edge tQUIET 200 ns min SCLK rising edge to rising edge tS 0.4 × tSCLK ns min SCLK low pulse width (space) tM 0.4 × tSCLK ns min SCLK high pulse width (mark) tSDO 8 ns max SCLK falling edge to SDO transition tSETUP 10 ns min SDI valid before SCLK rising edge tHOLD 10 ns min SDI valid after SCLK rising edge I2C With CS tied high to VDD I/O, the ADXL345 is in I2C mode, requiring a simple 2-wire connection as shown in Figure 8. The ADXL345 conforms to The I2C Bus Specification, Version 2.1, January 2000, available from Phillips Semiconductor. It supports standard (100 kHz) and fast (400 kHz) data transfer modes. Single or multiple byte read/writes are supported as shown in Figure 9. With the SDO pin high the 7 bit I2C address for the device is 0x1D, followed by the read/write bit. This translates to 0x3A for write, 0x3B for read. An alternate I2C address of 0x53 (followed by the read/write bit) may be chosen by grounding the SDO pin (pin 12). This translates to 0xA6 for write, 0xA7 for read. Figure 8. I2C Connection Diagram (Address = 0x53) If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDD I/O by more than 0.3 V. Pull-up resistors, RP, should be in the range of 1k to 20kΩ. Master Start Slave Address + Write Register Address Slave Ack Ack Ack Master Start Slave Address + Write Register Address Slave Ack Ack Ack Ack Master Start Slave Address + Write Register Address Start 1 Stop Slave Ack Ack Master Start Slave Address + Write Register Address Start 1 NAck Stop Slave Ack Ack 1This Start is either a restart or a Stop followed by a Start Data Stop Ack Single Byte Write Multi-Byte Write Data Data Multi-Byte Read Slave Address + Read Slave Address + Read Ack Data Data Data Stop NAck Ack Single Byte Read Figure 9. I2C Timing Diagram ADXL345 PROCESSOR CS SDA/SDI/SDIO D IN/OUT SDO SCL/SCLK D OUT RP RP VDD I/O 06238- 007 ADXL345 PROCESSOR CS SDA/SDI/SDIO D IN/OUT SDO SCL/SCLK D OUT RP RP VDD I/O 06238- 007 |
同様の部品番号 - ADXL345BCCZ-RL1 |
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同様の説明 - ADXL345BCCZ-RL1 |
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