5

FN8231.8

October 28, 2008

Timing Diagrams

Bus Timing

STOP Condition Set-up Time

From SCL rising edge crossing 70%

600

ns

STOP Condition Hold Time for

Read or Volatile Only Write

From SDA rising edge to SCL falling

600

ns

Output Data Hold Time

From SCL falling edge crossing 30%

0ns

Cpin

SDA and SCL Pin Capacitance

10

pF

13

Non-volatile Write Cycle Time

12

20

ms

10

SDA and SCL Rise Time

20 + 0.1xCb

300

ns

11, 13

SDA and SCL Fall Time

20 +0.1xCb

300

ns

11, 13

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

10

400

pF

11, 13

SDA and SCL Bus Pull-up Resistor

Off-chip

For Cb = 400pF, max is about

2k

Ω~2.5kΩ.

For Cb = 40pF, max is about

15k

Ω~20kΩ

1k

Ω

11, 13

NOTES:

7. Specified at +25°C.

9. Parameter is not 100% tested.

sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.

12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

13. Limits should be considered typical and are not production tested.

AC Electrical Specifications

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 12)

TYP

MAX

(Note 12)

UNITS

NOTES

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

ISL12026, ISL12026A