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SM3E-077.76M データシート(PDF) 9 Page - Connor-Winfield Corporation

部品番号 SM3E-077.76M
部品情報  ULTRA MINIATURE STRATUM 3E MODULE
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メーカー  CONNOR-WINFIELD [Connor-Winfield Corporation]
ホームページ  http://www.conwin.com
Logo CONNOR-WINFIELD - Connor-Winfield Corporation

SM3E-077.76M データシート(HTML) 9 Page - Connor-Winfield Corporation

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Data Sheet #: TM054
Page 9 of 36 Rev: 02
Date: 11/07/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Reference Input Quality Monitoring
Each reference input is monitored for signal presence and frequency offset. Signal presence for the Ref1-8 inputs is indicated in the
Ref_Activity register and signal presence for the M/S REF is indicated in bit 0 of the M/S REF_Activity register. The frequency offset
between the Ref1-8 inputs and the calibrated local oscillator is available in the Ref_Frq_Offset registers (8). Register Ref_Pullin_Sts
indicates, for each of the Ref1-8 inputs, if the reference is within the maximum pull-in range. The maximum pull-in range is indicated in
register Max_Pullin_Range, and may be set in 0.1ppm increments. Typically, it would be set according to the values specified by the
standards (GR-1244) appropriate for the particular stratum of operation.
The Ref_Qualified register contains the “anded” condition of the Ref_Activity and Ref_Pullin_Sts registers for each of the Ref1-8
inputs, qualified for 10 seconds. When a reference signal has been present for > 10 seconds and is within the pull-in range, it’s bit is set.
The Ref_Available register contains the “anded” condition of the Ref_Qualified register and the Ref_Mask register, and therefore
represents the availability of a reference for selection when automatic reference and operational mode selection is enabled.
Reference Input Selection, Frequencies, and Mode Selection
One of eight reference input signals (Ref 1-8) are selected for synchronization in Master mode (as below in the Op_Mode register
description. 0x05). Ref 1-8 may each be 8 kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or
77.76 MHz.
Reference frequencies are auto-detected and the detected frequency can be read from the Ref_Frq_Priority registers (See
Register Descriptions and Operation section).
Active reference and operational mode selection may be manual or automatic, as determined by bit 1 in the Ctl_Mode register. In
manual mode, register writes to Op_Mode select the reference and mode. The reset default is manual mode.
The M/S REF input for slave operation is frequency auto-detected and may be 8kHz, 1.544MHz, 2.048MHz, 12.96MHz, 19.44MHz,
25.92MHz, 38.88MHz, 51.84MHz or 77.76MHz. Signal presence and frequency for the M/S REF input is indicated in bits 0-3 of the M/S
REF_Activity register.
In automatic mode, the reference is selected according to the priorities written to the eight Ref_Frq_Priority registers. Individual
references may be masked for use/non-use according to the Ref_Mask register. A reference may only be selected if it is “available” -
that is, it is qualified, as indicated in the Ref_Qualified register, and is not masked (See Reference Input Quality Monitoring and
Register Descriptions and Operation sections).
Furthermore, Bit 3 of each Ref_Frq_Priority register will determine if that reference is revertive or non-revertive. When a reference
fails, the next highest priority “available” (signal present, non-masked, and acceptable frequency offset) reference will be selected.
When a reference returns, it will be switched to only if it is of higher priority and the current active reference is marked “Revertive”.
Additionally, the reversion is delayed according to the value written to the Ref_Rev_Delay register (From 0 to 255 minutes).
Detailed Description continued
Serial Interface Timing
Table 4
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
t
CS
SPI_Enable low to SPI_CLK low
15
-
-
ns
t
CH
SPI_CLK high time
25
-
-
ns
t
CL
SPI_CLK low time
25
-
-
ns
t
RWs
Read/Write setup time
15
-
-
ns
t
RWh
Read/Write hold time
15
-
-
ns
t
DRDY
Data ready
-
-
25
ns
t
HLD
Data Hold
15
-
-
ns
t
CSTRI
Chip Select to data tri-state
5
-
-
ns
t
CSMIN
Minimum delay between successive accesses300
-
-
ns
Note: The SPI port should not be accessed until 1200ms after reset has transitioned from low to a high state.


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