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TP2510 データシート(PDF) 1 Page - Supertex, Inc

部品番号 TP2510
部品情報  P-Channel Enhancement-Mode Vertical DMOS FETs
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メーカー  SUTEX [Supertex, Inc]
ホームページ  http://www.supertex.com
Logo SUTEX - Supertex, Inc

TP2510 データシート(HTML) 1 Page - Supertex, Inc

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11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
BVDSS /RDS(ON)
VGS(th)
ID(ON)
BV
DGS
(max)
(max)
(min)
TO-243AA*
Die
-100V
3.5Ω
-2.4V
-1.5A
TP2510N8
TP2510ND
* Same as SOT-89. Product supplied on 2000 piece carrier tape reels.
MIL visual screening available.
Ordering Information
Order Number / Package
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) tran-
sistors utilize a vertical DMOS structure and Supertex's well-
proven silicon-gate manufacturing process. This combination
produces devices with the power handling capabilities of bipolar
transistors and with the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic
of all MOS structures, these devices are free from thermal
runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very low
threshold voltage, high breakdown voltage, high input imped-
ance, low input capacitance, and fast switching speeds are de-
sired.
TP2510
Low Threshold
P-Channel Enhancement-Mode
Vertical DMOS FETs
Package Option
Features
❏ Low threshold — -2.4V max.
❏ High input impedance
❏ Low input capacitance — 125pF max.
❏ Fast switching speeds
❏ Low on resistance
❏ Free from secondary breakdown
❏ Low input and output leakage
❏ Complementary N- and P-channel devices
Applications
❏ Logic level interfaces – ideal for TTL and CMOS
❏ Solid state relays
❏ Battery operated systems
❏ Photo voltaic drives
❏ Analog switches
❏ General purpose line drivers
❏ Telecom switches
Absolute Maximum Ratings
Drain-to-Source Voltage
BVDSS
Drain-to-Gate Voltage
BV
DGS
Gate-to-Source Voltage
± 20V
Operating and Storage Temperature
-55°C to +150°C
Soldering Temperature*
300°C
* Distance of 1.6 mm from case for 10 seconds.
Note: See Package Outline section for dimensions.
G
D
S
TO-243AA
(SOT-89)
D
Product marking for TO-243AA
Where
❋ = 2-week alpha date code
TP5A


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