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EP2C8A15F324C8N データシート(PDF) 81 Page - Altera Corporation |
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EP2C8A15F324C8N データシート(HTML) 81 Page - Altera Corporation |
81 / 168 page Altera Corporation 3–7 February 2007 Cyclone II Device Handbook, Volume 1 Configuration & Testing Cyclone II Automated Single Event Upset Detection Cyclone II devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. Some applications that require the device to operate error free at high elevations or in close proximity to earth’s North or South Pole require periodic checks to ensure continued data integrity. The error detection cyclic redundancy code (CRC) feature controlled by the Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. You can implement the error detection CRC feature with existing circuitry in Cyclone II devices, eliminating the need for external logic. For Cyclone II devices, the CRC is pre-computed by Quartus II software and then sent to the device as part of the POF file header. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, indicating to the user to preform a device reconfiguration. Custom-Built Circuitry Dedicated circuitry in the Cyclone II devices performs error detection automatically. This error detection circuitry in Cyclone II devices constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a re-configuration cycle. You can select the desired time between checks by adjusting a built-in clock divider. Software Interface In the Quartus II software version 4.1 and later, you can turn on the automated error detection CRC feature in the Device & Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC checker between 400 kHz to 80 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. f For more information on CRC, refer to AN: 357 Error Detection Using CRC in Altera FPGAs. |
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同様の説明 - EP2C8A15F324C8N |
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