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EP2C8A15F324C8N データシート(PDF) 29 Page - Altera Corporation |
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EP2C8A15F324C8N データシート(HTML) 29 Page - Altera Corporation |
29 / 168 page Altera Corporation 2–17 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Each global clock network has a clock control block to select from a number of input clock sources (PLL clock outputs, CLK[] pins, DPCLK[] pins, and internal logic) to drive onto the global clock network. Table 2–2 lists how many PLLs, CLK[] pins, DPCLK[] pins, and global clock networks are available in each Cyclone II device. CLK[] pins are dedicated clock pins and DPCLK[] pins are dual-purpose clock pins. Figures 2–11 and 2–12 show the location of the Cyclone II PLLs, CLK[] inputs, DPCLK[] pins, and clock control blocks. Table 2–2. Cyclone II Device Clock Resources Device Number of PLLs Number of CLK Pins Number of DPCLK Pins Number of Global Clock Networks EP2C5 2 8 8 8 EP2C8 2 8 8 8 EP2C15 4 16 20 16 EP2C20 4 16 20 16 EP2C35 4 16 20 16 EP2C50 4 16 20 16 EP2C70 4 16 20 16 |
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