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EP20K400C データシート(PDF) 11 Page - Altera Corporation |
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EP20K400C データシート(HTML) 11 Page - Altera Corporation |
11 / 90 page Altera Corporation 11 APEX 20KC Programmable Logic Device Data Sheet The LAB-wide control signals can be generated from the LAB local interconnect, global signals, and dedicated clock pins. The inherent low skew of the FastTrack interconnect enables it to be used for clock distribution. Figure 4 shows the LAB control signal generation circuit. Figure 4. LAB Control Signal Generation Notes to Figure 4: (1) The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the LAB. (2) The SYNCCLR signal can be generated by the local interconnect or global signals. Logic Element The LE, the smallest unit of logic in the APEX 20KC architecture, is compact and provides efficient logic usage. Each LE contains a four-input LUT, which is a function generator that can quickly implement any function of four variables. In addition, each LE contains a programmable register and carry and cascade chains. Each LE drives the local interconnect, MegaLAB interconnect, and FastTrack interconnect routing structures. See Figure 5. SYNCCLR or LABCLK2 (2) SYNCLOAD or LABCLKENA2 LABCLK1 LABCLKENA1 LABCLR2 (1) LABCLR1 (1) Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect 4 4 |
同様の部品番号 - EP20K400C |
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同様の説明 - EP20K400C |
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