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SN74ACT3632 データシート(PDF) 8 Page - Texas Instruments |
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SN74ACT3632 データシート(HTML) 8 Page - Texas Instruments |
8 / 27 page SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FIFO write/read operation (continued) Table 3. Port-B Enable Function Table CSB W/RB ENB MBB CLKB B0 – B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L L L X X In high-impedance state None L L H L ↑ In high-impedance state FIFO2 write L L H H ↑ In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None L H H L ↑ Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high) The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setup- and hold-time window of the cycle. When a FIFO OR flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the OR flag high. When the OR flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port’s chip select, write/read select, enable, and mailbox select. synchronized FIFO flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. Table 4. FIFO1 Flag Operation NUMBER OF WORDS IN FIFO1†‡ SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA IN FIFO1†‡ ORB AEB AFA IRA 0 L L H H 1 to X1 H LH H (X1 + 1) to [512 – (Y1 + 1)] H HH H (512 – Y1) to 511 H HL H 512 H H L L † X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from port A. ‡ When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. |
同様の部品番号 - SN74ACT3632 |
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同様の説明 - SN74ACT3632 |
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